A low power low noise current starved CMOS VCO for PLL

In this article an ultra low power, low phase noise current starved CMOS VCO are proposed. This CSVCO is applicable for PLL application such as in, clock generation and recovery, frequency synthesizer for cell phones, fast locking in digital aid circuits etc. This proposed circuits area and power consumptions are very less and compatible for PLL applications. It demonstrates the superlative performance of the CSVCO. Transient response and phase noise analysis is performed and after simulation the phase noise at 1MHz is -104.0dBc/Hz with supply voltage of 1 V. It is performed using cadence virtuoso gpdk045 nm CMOS technology.