A low power low noise current starved CMOS VCO for PLL

Author

Saw, Suraj Kumar ; Nath, Vijay

Author_Institution

Dept. of ECE VLSI Design Group, Birla Inst. of Technol., Ranchi, India

fYear

2015

fDate

15-16 May 2015

Firstpage

1252

Lastpage

1255

Abstract

In this article an ultra low power, low phase noise current starved CMOS VCO are proposed. This CSVCO is applicable for PLL application such as in, clock generation and recovery, frequency synthesizer for cell phones, fast locking in digital aid circuits etc. This proposed circuits area and power consumptions are very less and compatible for PLL applications. It demonstrates the superlative performance of the CSVCO. Transient response and phase noise analysis is performed and after simulation the phase noise at 1MHz is -104.0dBc/Hz with supply voltage of 1 V. It is performed using cadence virtuoso gpdk045 nm CMOS technology.

Keywords

CMOS integrated circuits; frequency synthesizers; low-power electronics; phase locked loops; phase noise; synchronisation; transient response; voltage-controlled oscillators; PLL; cadence virtuoso gpdk; cell phones; clock generation; clock recovery; current starved CMOS VCO; digital aid circuits; frequency 1 MHz; frequency synthesizer; low phase noise current; low power low noise VCO; phase locked loop; size 45 nm; transient response; voltage 1 V; voltage control oscillator; CMOS integrated circuits; Charge pumps; Phase frequency detector; Phase locked loops; Phase noise; Voltage control; Voltage-controlled oscillators; Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOS); Current Starved Voltage Control Oscillator (CSVCO); low phase noise; phase locked loop (PLL); ultra low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing, Communication & Automation (ICCCA), 2015 International Conference on

Conference_Location

Noida

Print_ISBN

978-1-4799-8889-1

Type

conf

DOI

10.1109/CCAA.2015.7148611

Filename

7148611