DocumentCode
719537
Title
Improved Lateral Coupling Cell for a Standard Logic Process eNVM Application
Author
Kwang-Il Choi ; Nam-Yun Kim ; Sung-Kun Park ; In-Wook Cho
Author_Institution
Syst. IC Div., SK hynix Inc., Cheongju, South Korea
fYear
2015
fDate
17-20 May 2015
Firstpage
1
Lastpage
4
Abstract
In this paper, we describe a new single poly MTP (multiple time programmable) cell using contact plate and select gate coupling manufactured by 90 nm standard CMOS (complementary metal-oxide semiconductor) process. Proposed MTP cell size is smaller than conventional well coupled MTP cell and only select gate lateral coupling MTP cell in order to have the similar coupling ratio (CR) as the 1.98~3.26 μm2. The program erase operation use channel hot electron injection (CHEI) and band to band hot hole injection (BTBT-HHI). The cell performances are compared with splits group by coupling ratio (CR). Through the results represented by the experiments, we were able to achieve cell endurance of 100 cycle and 10 year retention lifetime at 150 °C, and realize operation margin with ease if coupling ratio is increased by adding plate contact. The describing cell using coupling of select gate and plate contact is thought to have more useful application due to technology shrink.
Keywords
CMOS memory circuits; hot carriers; CMOS process; band-to-band hot hole injection; channel hot electron injection; complementary metal oxide semiconductor; contact plate; eNVM application; embedded nonvolatile memory; lateral coupling cell; multiple time programmable cell; program erase operation; select gate coupling; single poly MTP; standard logic process; Couplings; Degradation; EPROM; Logic gates; Nonvolatile memory; Periodic structures; Standards;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop (IMW), 2015 IEEE International
Conference_Location
Monterey, CA
Print_ISBN
978-1-4673-6931-2
Type
conf
DOI
10.1109/IMW.2015.7150289
Filename
7150289
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