DocumentCode :
719547
Title :
Performance Characterization of LDPC Codes for Large-Volume NAND Flash Data
Author :
Khayat, Patrick ; Kaynak, Mustafa ; Parthasarathy, Sivagnanam ; Sharifi Tehrani, Saeed
Author_Institution :
Micron Technol., Inc., San Diego, CA, USA
fYear :
2015
fDate :
17-20 May 2015
Firstpage :
1
Lastpage :
4
Abstract :
High bit error rates of next-generation flash devices necessitate the use of more powerful error correction codes (ECCs), such as low-density parity-check (LDPC) codes, instead of the legacy Bose-Chaudhuri-Hocquenghem (BCH) codes. Unlike algebraic codes, the random nature of LDPC codes as well as their ability to use soft information requires the use of Monte Carlo (MC) simulations to evaluate code performance. Given a large volume of NAND data, this can pose resource challenges both in terms of simulation platforms and time needed for the Monte Carlo simulations. In order to overcome these challenges, we introduce a new channel metric in this paper to quantify the quality of soft information and propose a practical LDPC code performance characterization methodology.
Keywords :
BCH codes; Monte Carlo methods; error correction codes; error statistics; flash memories; parity check codes; BCH codes; Bose-Chaudhuri-Hocquenghem codes; ECC; LDPC codes; MC simulations; Monte Carlo simulations; NAND flash data; bit error rates; channel metric; error correction codes; low-density parity-check codes; next-generation flash devices; soft information; Decoding; Error correction codes; Flash memories; Measurement; Parity check codes; Reliability; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Memory Workshop (IMW), 2015 IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4673-6931-2
Type :
conf
DOI :
10.1109/IMW.2015.7150301
Filename :
7150301
Link To Document :
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