DocumentCode :
719552
Title :
Technology Scaling Challenge and Future Prospects of DRAM and NAND Flash Memory
Author :
Sung-Kye Park
Author_Institution :
Device & Process Integration Technol. Group, SK hynix Inc., Icheon, South Korea
fYear :
2015
fDate :
17-20 May 2015
Firstpage :
1
Lastpage :
4
Abstract :
Memory manufactures are facing the challenges of technology scaling beyond 1xnm node DRAM and NAND flash memory. Even though we are managing to overcome patterning issue, we are still fighting against cost reduction and electrical limitation. In this paper, the scaling limitations and challenges of both DRAM and NAND are reviewed, and the future prospects with promising solutions are also addressed for high density DRAM and 3D NAND flash memory.
Keywords :
DRAM chips; NAND circuits; flash memories; logic design; nanopatterning; three-dimensional integrated circuits; 3D NAND flash memory; DRAM; cost reduction; electrical limitation; memory manufactures; patterning; technology scaling; Flash memories; Logic gates; Random access memory; Reliability; Sensors; Three-dimensional displays; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Memory Workshop (IMW), 2015 IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4673-6931-2
Type :
conf
DOI :
10.1109/IMW.2015.7150307
Filename :
7150307
Link To Document :
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