Performance enhancement of InGaAs MOSFET using trench technology

Author

Adhikari, Manoj Singh ; Singh, Yashvir

Author_Institution

Dept. of Electron. & Commun. Eng., G. B. Pant Eng. Coll., Pauri Garhwal, India

fYear

2015

fDate

16-18 March 2015

Firstpage

309

Lastpage

311

Abstract

A high-performance In_0.53 Ga_0.47As n-channel MOS-FET by incorporating trench into planner technology is presented. The device has 40 nm gate length with 6 nm high-k HfO₂ gate oxide thickness. The TaN gate electrode is placed in a trench built in epitaxial layer so that two channels are created in p-base. Source and drain contacts are located symmetrically on both sides of gate electrode. Two-dimensional numerical simulations are performed to analyse and compare the performance of the proposed MOSFET with that of the conventional MOSFET. The proposed MOSFET provides 5.3 times improvement in both output current and peak transconductance and 78% higher unity current gain cut-off frequency (f_T) when compared with that of the conventional MOSFET.

Keywords

III-V semiconductors; MOSFET; electrodes; epitaxial layers; gallium arsenide; hafnium compounds; indium compounds; isolation technology; numerical analysis; semiconductor device models; tantalum compounds; 2D numerical simulations; HfO₂; In_0.53Ga_0.47As; TaN; drain contacts; epitaxial layer; gate electrode; high-k gate oxide thickness; n-channel MOSFET; p-base; planner technology; size 40 nm; size 6 nm; source contacts; transconductance; trench technology; unity current gain cut-off frequency; Cutoff frequency; Indium gallium arsenide; Logic gates; MOSFET; Performance evaluation; Threshold voltage; Transconductance; InGaAs; MOSFET; cut-off frequency; transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing and Communication (ICSC), 2015 International Conference on

Conference_Location

Noida

Print_ISBN

978-1-4799-6760-5

Type

conf

DOI

10.1109/ICSPCom.2015.7150667

Filename

7150667