Comparative analysis of single mode and multimode QC-LDPC decoder using modified belief propagation algorithm

Low density parity check codes (LDPC) are appearing in an increasing number of applications which shows a performance close to the Shannon limit. The near Shannon limit error correction capability has lead LDPC codes to become the coding technique of choice in many communications and storage systems since their introduction. LDPC have good error correcting performance which enables efficient and reliable communication. Quasi-cyclic LDPC codes known as a subclass of LDPC codes are used whose parity check matrices consists of circulant permutation matrices. This character of QC-LDPC codes opens the door for the multi-mode. In the present work partially parallel architecture for single mode and multi-mode quasi-cyclic low density parity check (QC-LDPC) decoders have been designed using modified belief propagation algorithm. QC-LDPC codes require less memory as compared to LDPC codes and resource occupied by the single mode decoder is only a little more than the multi-mode decoder. This decoder is modeled using Verilog software, synthesized and performed place and route for the design using Xilinx ISE 13.2.