A low-power interface circuit for piezoresistive transducers

Author

Donida, Achille ; Barrettino, Diego

Author_Institution

Dept. of Technol. & Innovation (DTI), Univ. of Appl. Sci. of Southern Switzerland, Manno, Switzerland

fYear

2015

fDate

11-14 May 2015

Firstpage

1774

Lastpage

1778

Abstract

This paper presents the design and development of a low-power interface circuit for piezoresistive transducers. This circuit combines the chopping technique with the correlated double sampling (CDS) technique in order to eliminate both the amplifier offset and the chopper ripple at the sampling frequency. In addition, programmable current sources compensate for the transducer offset and the low frequency components coming from environmental conditions thus allowing the readout of very weak input signals with high resolution (0.45μV) at a total power consumption of 200 μW.

Keywords

choppers (circuits); piezoelectric transducers; piezoresistive devices; power consumption; sampling methods; amplifier offset; chopper ripple; chopping technique; correlated double sampling technique; low-power interface circuit; piezoresistive transducers; power 200 muW; power consumption; programmable current source; sampling frequency; voltage 0.45 muV; CMOS integrated circuits; Choppers (circuits); Frequency modulation; Noise; Piezoresistance; Resistors; Transducers;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference (I2MTC), 2015 IEEE International

Conference_Location

Pisa

Type

conf

DOI

10.1109/I2MTC.2015.7151549

Filename

7151549