A systematic study of layout proximity effects for 28nm Poly/SiON logic technology

Author

Ruoyuan Li ; Jiajia Tao ; Tao Yang ; Zicheng Pan ; Yuejiao Pu ; Hong Wu ; Yu Shaofeng ; Falong Zhou ; Yongping Deng ; Ling Sun ; Longyi Yue ; Fengying He ; Weizhong Xu ; Ye Bin ; Yu TzuChiang

Author_Institution

Technol. R&D Center, SMIC, Shanghai, China

fYear

2015

fDate

15-16 March 2015

Firstpage

1

Lastpage

4

Abstract

As CMOS scaling extends into 28nm technology, transistor behavior depends not only on its channel length and width, but also on other layout geometric parameters and the surrounding neighborhood. In this paper, a systematic study was conducted on the layout proximity effects (LPEs) of 28nm Poly/SiON logic transistors, which includes length of oxide diffusion (LOD) effect, dummy poly spacing (DPS) effect, active area spacing effect (ASE), and well proximity effect (WPE). We explored the mechanisms behind these LPEs and proposed physical models that can explain the LPEs´ impacts on transistor electrical behavior. We found that the changes in dopant distribution and stress/dopant induced mobility at different transistor geometric parameters are the two major factors that cause LPEs.

Keywords

CMOS logic circuits; proximity effect (lithography); silicon compounds; CMOS scaling; active area spacing effect; dopant distribution; dummy poly spacing effect; layout proximity effects; length of oxide diffusion effect; logic technology; logic transistors; transistor electrical behavior; well proximity effect; Compressive stress; MOS devices; Market research; Performance evaluation; Silicon; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Technology International Conference (CSTIC), 2015 China

Conference_Location

Shanghai

ISSN

2158-2297

Type

conf

DOI

10.1109/CSTIC.2015.7153318

Filename

7153318