New Pcell based ring oscillator layout auto-generation method and application in advanced SPICE model verification

A fast Parametric Cell based ring oscillator layout generation approach is proposed. By using hierarchical Pcell structures, different types of gate, INV, NOR, NAND, with variant stage number and different sizes can be generated automatically. The Pcell is especially designed for advanced CMOS technology, as ring oscillators are good verification vehicle for many advanced IV/CV layout dependent effects (LDE). We demonstrate this by measuring different ring oscillator delay periods for Contact-Gate space change. It shows that the contact parasitic capacitance is reflected to gate delay correctly. The approach is highly promising for future SPICE model verification with a large number of ring oscillator designs.