Challenges and solutions to FinFET gate etch process

When CMOS technologies entered nanometer scales, FinFET has become one of the most promising devices because of its superior electrical characteristics. To accommodate the 3D topography, gate etch needs soft landing on the top of Fin while removing the extra poly-si around Fin. Its over etch is more aggressive than conventional planar gate to avoid poly-si residue. Fin loss should be well controlled because it will adversely affect device performance. Besides, the gate profile control is also one big challenge for FinFET gate etch. We found the amorphous poly-si etching with plasma pulsing can balance Fin top loss and gate profile control. The optimized pulsing parameters could deliver the preferred slightly notched profile. This will benefit the following metal gate fabrication. Furthermore, Line end-to-end space CD shrink is another challenge for FinFET gate etch. SO2 based plasma for mask opening exhibits the promising CD shrinkage capability.