• DocumentCode
    720794
  • Title

    The optimization of post etch treatment for Contact Etch process

  • Author

    Jing-yong Huang ; Qi-yang He ; Hai-Yang Zhang

  • Author_Institution
    Technol. R&D, Semicond. Manuf. Int. Corp., Shanghai, China
  • fYear
    2015
  • fDate
    15-16 March 2015
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    Since CMOS technology moved to sub-40nm node and beyond, the remarkable challenges have been noticed in dry etch, wet clean and the subsequent metal deposition process of contact loop. Contact etch has been proven as one of the most critical roles for yield enhancement. It not only needs to overcome the incoming challenges such as poor PR profile/CDU and CESL (Contact Etch Stop Layer) nitride pinch-off, but also needs to deliver the post etch treatment process to enlarge the process window of the subsequent wet clean and metal deposition steps. Due to the high selectivity and large CD shrink gap from litho to etch, it is requested to employ the polymer rich etch process, followed by stronger polymer removal wet clean step in contact loop. However, because of the small CD and the high aspect ratio of contact hole, it is very difficult to remove the polymer deposited at the bottom of contact hole by single wafer wet clean process. Furthermore, the polymer residue easily leads to the metal void or blocks the metal formation in the subsequent metal deposition step. This is one major yield killer. This paper focused on the post etch treatment process by the optimization with uniform design DOE for etch parameters, and aims to enlarge the whole process window in contact loop for final yield enhancement.
  • Keywords
    CMOS integrated circuits; etching; integrated circuit yield; polymers; voids (solid); CD shrink gap; CESL; CMOS technology; contact etch process; contact etch stop layer; contact hole; contact loop; metal deposition; metal void; nitride pinch-off; polymer removal wet clean step; polymer residue; polymer rich etch process; poor PR profile; post etch treatment optimization; process window; yield enhancement; Analytical models; Data models; Metals; Polymers; Silicides; Surface resistance; Yield estimation; Contact etch; orthogonal design DOE; polymer removal; post etch treatment; yield enhancement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Technology International Conference (CSTIC), 2015 China
  • Conference_Location
    Shanghai
  • ISSN
    2158-2297
  • Type

    conf

  • DOI
    10.1109/CSTIC.2015.7153389
  • Filename
    7153389