Challenges and solutions for 14nm FinFET etching

Author

Huang Jun ; Li Quanbo ; Chong Ermin ; Yi Chunyan ; Li Runling ; Gai Chenguang ; Ma Zhibiao ; Yu Zhang ; Pang, Albert

Author_Institution

TD II, Shanghai Huali Microelectron. Corp., Shanghai, China

fYear

2015

fDate

15-16 March 2015

Firstpage

1

Lastpage

4

Abstract

The gate for FinFET structure is graved into a 3D architecture just as a fin fork so that we can control device on/off through the surfaces of its top and two sides. Such design can greatly improve the controllability of circuit and reduce leakage and shorten gate length. Although FinFET has so many advantages, such as lower power, smaller size and etc., it brings big challenges to process, especially to etching process. This paper will analyze the main challenges and solutions for 14nm FinFET etching, including intracell depth loading, profile and angle control of Fin/STI/Gate, Spacer etching, residue control, CD loading and CD uniformity control.

Keywords

MOSFET; etching; isolation technology; 3D architecture; CD loading; CD uniformity control; FinFET etching; STI; angle control; circuit controllability; gate length; intracell depth loading; leakage reduction; residue control; shallow trench isolation; size 14 nm; spacer etching; Loading; Logic gates;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Technology International Conference (CSTIC), 2015 China

Conference_Location

Shanghai

ISSN

2158-2297

Type

conf

DOI

10.1109/CSTIC.2015.7153391

Filename

7153391