Investigation and solution of intermittent GOI failures at 40 nm CMOS devices

Low k (dielectric constant) barrier (SiCN) is one of the most critical dielectric films used in Cu interconnects, and it has great impact on device reliability such as gate oxide integrity (GOI), plasma induced damage (PID), time-dependent dielectric breakdown (TDDB), electromigration (EM) and so on. This work was to investigate an intermittent GOI failure at 40nm CMOS devices, which was caused by low-k Cu barrier film deposition, and develop an improved process to resolve this issue. To understand the GOI failures, surface charge was collected at various process conditions. It was found, however, that the processes with the lowest surface charge and the best charge non-uniformity didn´t improve GOI unexpectedly. The GOI issue was resolved instead by optimizing the RF ramp-up setting and inserting a novel enhanced nitride interface (ENI) layer (~30A). Further studies found that the GOI damage was primarily formed during the plasma ignition step and was related to instantaneous plasma non-uniformity. Well controlled plasma ignition and better Cu surface protection were the keys to achieve good GOI performance.