Case study of reducing excursion yield loss

Traditionally, the foundry is responsible for yield enhancement when excursion yield loss occurs. Sometimes the cycle time to fix the problems is too long and can be unpredictable due to a lack of design details and process uncertainty on the foundry side. In order to reduce overall cycle time for fixing excursion yield loss, the fabless company can give the foundry insightful information of defect localization that can be used for analysis to avoid unnecessary iterations. Various approaches for obtaining useful information to the foundry are possible and the ultimate goal is to find the optimal methodology as a long-term solution. The main motivation is cost; yield loss can make a huge bottom-line impact, especially for high volume product. This paper demonstrates a case study of yield ramp for a real production chip and highlights the importance of an efficient approach based on a scan diagnosis methodology.