An optimized and unified system for FPGA power-up validation to minimize post-silicon cycling time

Power-up validation is a critical process in R&D of FPGA, since it will determine if a FPGA can work correctly at the very first step of operation. Power-up validation includes 4 separate blocks. Testing each block one by one couldn´t meet today´s short time-to market requirement for a new product. In this paper, an optimized and unified system is proposed to perform validation for all power-up items. The validation efficiency was improved by several times comparing to the traditional approach. The experimental results indicate nearly 90% test time can be saved for the power-up validation.