Time optimization of instruction execution in FPGA using embedded systems

This paper presents a method to implement time optimization of instructions in Field Programmable Gate Array (FPGA) using application of embedded systems. The proposed technique is intended to reduce the time of processing of instructions inside a processor and ATMega328 microcontroller is used for this purpose. An algorithm has been proposed to predict the most suitable processor architecture which should be preferably used to iteratively execute the instructions. This prediction, along with the input of instructions to the FPGA, is done by the microcontroller and the same is transferred to the FPGA using suitable interfacing technique. Two architectures are intertwined and burnt on the microprocessor chip of the FPGA beforehand. Proteus VSM has been used for simulation of the embedded portion of the system and the processor architectures are designed in Xilinx ISE v13.4 and simulated in ISIM simulator.