Implementing PSK MODEMs on FPGA Using Partial Reconfiguration

The radio, which has as many as components with programmable devices, was envisioned as future of telecommunication industry by Joseph Mitola in 1991. The traditional, bulky and costly radios are expected to be replaced by a radio in which properties of carrier frequency, signal bandwidth, modulation and network access are defined in software. The key requirements for SDR platforms are flexibility, expandability, scalability, re-configurability and re-programmability. In SDR, the power consumption, configuration time, hardware usage plays significant role. FPGA has both high speed processing capability and good reconfigurable performance hence FPGA architecture is a viable solution for SDR technology The objective of this paper is to demonstrate simulation and implementation of the PSK modems on FPGA using Partial Reconfiguration. By using Partial Reconfiguration (PR) technique the hardware usage, configuration time and power consumption can be reduced. The PSK modulator and demodulator algorithms are simulated using MATLAB R2013a and implemented on FPGA using Xilinx ISE 14.2 System Generator, PlanAhead, Partial Reconfiguration Tool. The results indicate Partial Reconfiguration design leads to negligible reconfiguration time saving in resource utilization by 55%, in power consumption by 75%. The output waveforms are displayed and analyzed using Xilinx ChipScope Pro. The output waveforms are displayed and analyzed using Xilinx ChipScope Pro.