DocumentCode :
723070
Title :
Silicon interposer and TSV signaling
Author :
Martwick, Andrew ; Drew, John
Author_Institution :
Intel Corp., Hillsboro, OR, USA
fYear :
2015
fDate :
26-29 May 2015
Firstpage :
266
Lastpage :
275
Abstract :
Silicon interposers and through silicon vias are new technologies that are currently being readied for production. This research examines the electrical and timing models to predict how fast this technology will scale. We show that the metrics first introduced by W.C. Elmore to the delay and bandwidth calculations of cascaded low pass elements provide excellent predictions for the interconnect signal integrity. By applying a simple transmit equalizer we show that 6 mm links will scale to over 6 Gb/s. To support the scaling calculations we review the timing jitter model that is used to calculate the timing budget at the receiver to achieve a 0 bit error rate. This technology requires such a detailed model because the geometry is too small to allow direct measurements, it must be guaranteed by design and confirmed by margin testing.
Keywords :
cascade networks; error statistics; integrated circuit interconnections; integrated circuit modelling; integrated circuit testing; silicon; three-dimensional integrated circuits; timing jitter; TSV signaling; bit error rate; cascaded low pass elements; electrical models; interconnect signal integrity; margin testing; silicon interposer; size 6 mm; through silicon vias; timing budget; timing jitter model; transmit equalizer; Bandwidth; Bit error rate; Capacitance; Mathematical model; Receivers; Silicon; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location :
San Diego, CA
Type :
conf
DOI :
10.1109/ECTC.2015.7159603
Filename :
7159603
Link To Document :
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