The mechanism and kinetic study of void migration in Cu vias under current flow by 3D X-ray computed tomography

Miniaturization and portability of consumer electronics is driving the substrate technology to enable packages with higher circuit density, smaller size, and lower Z height. Cu vias with large aspect ratio are being used for these next generation substrate technologies. Due to the relatively large aspect ratio of the Cu vias, voids could form during the electrolytic Cu filling process. To understand the void behavior under current flow, samples are subjected to high current at elevated temperatures. 3D X-ray computed tomography is used to characterize these voids in Cu vias before and during the test at intermediate readouts. These studies find that the voids accumulate and migrate preferentially to the applied bias polarity. The hypothesis of the void movement under current flow is discussed and the kinetics of the void migration is proposed with the estimations of activation energy and current density exponent.