Quantifying impact of design parameters on Ultra-Low k ILD reliability in fine pitch Cu bump interconnect structures

Increasing feature integration into mobile processors and high performance require denser IO as well as more power/ground pin count. Specifically DDR speed is one of the major drivers for more IO which is realized by aggressively reducing bump pitch. Cu interconnect as well as ULK (Ultra-Low k) dielectric is introduced for such fine pitch processors at advanced Silicon nodes, and the reliability of ULK dielectric is the key concern of CPI (Chip Package Interaction). Since the bump cell size has to be reduced at fine pitch, the thermal-mechanical stress in ULK due to packaging assembly process increases significantly. Robust CPI solutions that address ULK reliability have to be defined at each Si technology node with sufficient margin to cover process variations and provide design flexibility. In this paper, we summarize our findings about impacts of design parameters on ULK reliability. First, since the mechanical stress is approximately inversely proportional to unit bump cell size, experimental study is carried out with various bump cell size at process corner conditions. Bump cell with circular shaped UBM that meets both assembly and CPI requirements without adversely affecting the design space is successfully developed for fine pitch applications. Our data shows reducing bump cell size further will increase CPI risk significantly, and may not be suitable for certain package configurations. Second, bump cell with non-circular shaped UBM is investigated to meet even tighter fine pitch requirement. Data suggests it is critical to understand the ULK reliability impact of both bump cell size as well as orientation of UBM major axis due to its non-circular shape. It is found that, with proper design guidelines, non-circularshaped bump cell can greatly improve CPI margin compared to circular-shaped ones. Third, impact of bump density and die size are studied using thermal shock testing and numerical simulation. It is found that, at design stage, global as well as loca- UBM density near die corner and periphery area must be carefully considered to prevent any ULK delamination. Impact of die size due to DNP effect is also discussed. Numerical simulation is used in this paper to simulate mechanical stress in ULK dielectric material during packaging assembly process. It is necessary to include Si BEOL stackup, correct material properties and detailed Cu bump interconnect structures in the model for accuracy. However, due to the complexity and length-scale range of BEOL stackup, it is not possible to capture all the details in numerical models. Assumptions and simplifications must be made in the model on various geometry and material parameters including BEOL stackup. Metal, oxide as well aspassivation layer properties need to be smeared using composite material principles. Different material and metal/ILD layer homogenization techniques of BEOL are tested numerically in this work. A paper study comparing mechanical stress of two different BEOL stackup using those homogenization techniques is presented. Further, impact of BEOL metal layers on ULK reliability is studied using simulation, and overall trend is summarized.