The impact and performance of electromigration on fine pitch Cu pillar with different bump structure for flip chip packaging

The electromigration (EM) behavior and performance of solder capped Cu pillar assembled with bump on trace (BOT) processed by mass reflow is measured and analyzed. The interconnections with two different Cu pillar bump structures were tested: Cu post + SnAg solder tip and Cu post + Ni barrier +SnAg solder tip. Emphasis is placed on the EM impact and performance of the two different Cu pillar bump structures. The test temperature ranged from 130-150°C and the current of 500-900mA was applied, which is corresponding to the current density 25-45kA/cm². The substrate side finish is organic solderability preservative (OSP) on Cu trace. The Cu pillar bump pitch is 87μm and the bump size is 50μm. Some important results are summarized in the following.The MTTF of electromigration life of Cu pillar BOT with Ni barrier layer legs are better than that of no Ni barrier layer legs among different EM test conditions. As compared to typical lead-free bump EM performance in the same test condition, Cu pillar BOT without Ni barrier performs better MTTF life even though the current density input is 5X higher than lead-free bump with tightened criteria. The EM data of Cu pillar BOT with or without Ni barrier legs approved robust performance to meet fine pitch high performance packages requirement. The failure mode of Cu pillar BOT without Ni barrier layer showed obviously Cu post and trace consumption, Kirkendall void/cracks were formed in the interface between (Cu)3Sn IMC/Cu post and (Cu)3Sn IMC/Cu trace. While in substrate trace side of Cu pillar BOT with Ni layer, a large part of Cu trace was consumed and transformed into CuSn IMC. Crack between (Cu)3Sn and Cu trace or Cu trace crack were observed and caused the EM failure.