Title :
Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV
Author :
Sugawara, Yohei ; Hashiguchi, Hideto ; Tanikawa, Seiya ; Kino, Hisashi ; Kang-Wook Lee ; Fukusima, Takafumi ; Koyanagi, Mitsumasa ; Tanaka, Tetsu
Author_Institution :
Dept. of Bioeng. & Robot., Tohoku Univ., Sendai, Japan
Abstract :
3D-IC (3D-stacked integrated circuit) requires lots of through-Si vias (TSVs) and metal microbumps for electrical connection among stacked LSI chips to realize higher performance beyond 2D-IC. However, plasma etching process for via-last backside TSV formation could damage many transistors used in the 3D-IC. In this study, plasma-induced charge-up damages on transistor characteristics during viahole etching have been investigated using test structures flipchip bonded on Si interposer. Additionally, antenna rules for the 3D-IC layout and process design were also mentioned.
Keywords :
sputter etching; three-dimensional integrated circuits; 3D-IC; 3D-stacked integrated circuit; deep-via plasma etching process; electrical connection; metal microbumps; plasma-induced charge-up damages; via-last backside TSV; Etching; Integrated circuits; Logic gates; MOSFET; Metals; Silicon; Wiring;
Conference_Titel :
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location :
San Diego, CA
DOI :
10.1109/ECTC.2015.7159687
