• DocumentCode
    723098
  • Title

    A flexible interconnect technology demonstrated on a wafer-level chip scale package

  • Author

    Yang, S.C. ; Wu, C.J. ; Hsiao, Y.L. ; Tung, C.H. ; Yu, Doug C. H.

  • Author_Institution
    TSMC R & D, Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan
  • fYear
    2015
  • fDate
    26-29 May 2015
  • Firstpage
    859
  • Lastpage
    864
  • Abstract
    In this paper, a flexible interconnect technology, including Cu wire bonding and pre-solder was proposed and demonstrated in 200 mm2 WLCSP. Flexible interconnects were fabricated by a modified industry wire bonder with good position accuracy and height uniformity. Different wire geometries were created. In addition, influence of wire material, die thickness and solder volume is also investigated. Chips with more than 1000 interconnects were directly mounted on PCB and underfill is not used after assembly process. All assembled units were subjected to the board level reliability thermal cycling test according to JEDEC standard. Some of them were also subjected to drop tests. Both experimental and finite element analysis have demonstrated that flexible interconnects can greatly improve the thermal mechanical reliability and survived over 500 cycles without underfill. In the drop test, N-shape interconnects have better performance than I-shape interconnects and pass over 30 drops. This flexible interconnection technology can lead to excellent reliability in larger WLCSPs without the use of underfill. In addition, this flexible interconnect could be applied in a fine pitch PoP and the number of I/O pads can be increased without modifying the package structure.
  • Keywords
    chip scale packaging; copper; finite element analysis; integrated circuit interconnections; lead bonding; mechanical stability; printed circuits; solders; thermal stability; wafer level packaging; Cu; I-shape interconnect; I/O pads; JEDEC standard; N-shape interconnect; PCB; WLCSP; assembly process; board level reliability thermal cycling test; copper wire bonding; die thickness; drop test; fine pitch PoP; finite element analysis; flexible interconnect technology; printed circuit board; solder volume; thermal mechanical reliability; underfill; wafer-level chip scale package; wire geometry; wire material; Electronic components; Integrated circuit interconnections; Reliability; Shape; Soldering; Stress; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
  • Conference_Location
    San Diego, CA
  • Type

    conf

  • DOI
    10.1109/ECTC.2015.7159693
  • Filename
    7159693