• DocumentCode
    723100
  • Title

    Copper foil exposed structure for thin PoP warpage improvement

  • Author

    YeSeul Ahn ; JinSeong Kim ; ChaGyu Song ; GyuWan Han ; JuHoon Yoon ; ChoonHeung Lee

  • Author_Institution
    R&D Center, Amkor Technol. Korea Inc., Seoul, South Korea
  • fYear
    2015
  • fDate
    26-29 May 2015
  • Firstpage
    877
  • Lastpage
    881
  • Abstract
    Advanced flip chip packaging technology supports the next generation of products with increased die complexities. The increase in complexity and functionality has been driving the need to investigate fine-pitch interconnection technology with 3D integration. Recently, Package on Package (PoP) has emerged as the preferred 3D integration of logic processors and memory devices for mobile handsets and portable applications. The current PoP solution consists of memory die in the top package stacked on logic function die in the bottom package. Various challenges also need to be met to support the volume production and establish reliable manufacturing process for PoP platform. Among the available key technologies, the TMV (Through Mold Via) solution has been widely adopted to reduce package warpage, achieve a fine-pitch PoP and stabilize stacking performance. Furthermore, since the trend towards thinner phones continues, it is essential to reduce the thickness of PoP to meet market requirement. However, controlling warpage is one of main concerns to generate a thin PoP TMV structure. In this paper, a copper foil exposed package, which has a thin copper foil with adhesive layer film, is introduced as a new PoP bottom package structure. It was laminated on the die backside to improve warpage behavior at room and evaluated temperatures. Based on simulation and experimental results, it was concluded warpage amount and direction depend on thickness and thermo mechanical properties of the copper foil as well as the adhesive material. The best combination was selected for best warpage behavior not only for the bottom package but also PoP stacked warpage to see if it could improve high package stacking yield performance.
  • Keywords
    adhesives; copper; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; integrated memory circuits; logic circuits; mobile handsets; three-dimensional integrated circuits; 3D integration; TMV; adhesive layer film; advanced flip chip packaging technology; copper foil exposed structure; die complexity; fine-pitch interconnection technology; logic function die; logic processor; manufacturing process; memory device; memory die; mobile handset; package on package; package stacking; package warpage reduction; portable application; thermomechanical property; thin PoP warpage improvement; through mold via; Copper; Electronic components; Films; Stacking; Substrates; TV; Vehicles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
  • Conference_Location
    San Diego, CA
  • Type

    conf

  • DOI
    10.1109/ECTC.2015.7159696
  • Filename
    7159696