Fast thermal coupling simulation of on-chip hot interconnect for thermal-aware EM methodology

For advanced process technologies as in FinFET or FDSOI, the current density increases while the wire width and spacing get reduced, leading to higher ΔT on wires due to self-heating and strong thermal coupling among wires. This impacts chip reliability and performance. Also, since the traditional methodology of using a uniform worst-case temperature across a chip for electromigration (EM) sign-off is often too pessimistic, or could fail to take into account a thermal hotspot, it is necessary to estimate the realistic temperature of wires to ensure reliability while optimizing the wire design. Due to the large number of wires in a modern chip, application of a direct thermal field solution such as FEM (finite element method) with all wires considered is not feasible. On the other hand, this paper describes an innovative method where the temperature increases on millions of wires due to self-heat are efficiently and accurately calculated. Also outlined is the thermal-aware EM methodology that considers both Chip-package-system (CPS) thermal environment and self-heat.