Title :
Fabrication of ultra-fine vias in low CTE Build-up Films using a novel dry etching technology
Author :
Morikawa, Yasuhiro ; Sato, Muneyuki ; Sakao, Yosuke ; Fujinaga, Tetsushi ; Tani, Noriaki ; Saito, Kazuya
Author_Institution :
Inst. of Semicond. & Electron. Technol., ULVAC Inc., Chigasaki, Japan
Abstract :
An ultra-fine vias pattern below 10 μm with low surface-roughness in a low-CTE Build-up film was achieved by a new fabrication. In this method, a DFR (Dry Film Resist) mask was formed on ABF (Ajinomoto Build-up Film) by the photolithography process. There were achieved ultra-fine vias through the use of a dry etching method. In the last years the number of high performance mobile devices, such as smart phones or tablet PCs, increases widely and accordingly data traffic augments rapidly. Devices for these equipments require high-rate processing capabilities, high-density packaging possibilities and low power consumptions. Thus the demand for packed semiconductor chips with high density of components is growing. In order to accomplish high-density packaging, miniaturization of wiring in organic package is needful. To obtain vias in a build-up film, the laser drilling process is widely used but there are three major restricting difficulties. The first is that it is impossible to make ultra-fine vias because of laser wave length limitation. The second is that wet desmear process to remove residuals is necessary. Finally, film surface gets rough when wet desmear is used and hence the performances of devices in high frequency are affected.
Keywords :
laser beam etching; laser beam machining; low-power electronics; masks; photolithography; resists; semiconductor device packaging; surface roughness; thermal expansion; three-dimensional integrated circuits; Ajinomoto build-up film; data traffic; dry etching technology; dry film resist mask; high performance mobile devices; high-density packaging possibility; high-rate processing capability; laser drilling process; laser wavelength limitation; low CTE build-up films; low power consumptions; organic package; packed semiconductor chips; photolithography process; surface roughness; ultra-fine vias fabrication; ultra-fine vias pattern; wet desmear process; wiring miniaturization; Etching; Fabrication; Films; Plasmas; Rough surfaces; Silicon compounds;
Conference_Titel :
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location :
San Diego, CA
DOI :
10.1109/ECTC.2015.7159795