DocumentCode
723163
Title
A systematic exploration of the failure mechanisms in underfilled flip-chip packages
Author
Sinha, Tuhin ; Davis, Taryn J. ; Lombardi, Thomas E. ; Coffin, Jeffery T.
Author_Institution
IBM Syst., Hopewell Junction, NY, USA
fYear
2015
fDate
26-29 May 2015
Firstpage
1509
Lastpage
1517
Abstract
A study on failure mechanisms in underfilled flip-chip packages is presented here. The flip-chip packages were built after conducting a range of finite element modeling studies that varied only the geometric entities in the package. Thereafter, these packages were stressed under a thermal-cyclic loading condition and were probed for electrical failures during the course of thermal cycling. The finite element analysis´ thermal cyclic modeling simulations show a good correlation between the predicted plastic-energy dissipation per unit volume in the solder stack and the measured electrical and physical failures in the packages. The empirical correlations developed in this study can be extended to a generic package for predicting the failures associated with reliability either during testing or under field operating conditions.
Keywords
failure analysis; finite element analysis; flip-chip devices; solders; thermal analysis; electrical failures; failure mechanisms; finite element analysis; finite element modeling; plastic-energy dissipation; solder stack; thermal cyclic modeling simulations; thermal cycling; thermal-cyclic loading condition; underfilled flip-chip packages; Assembly; Failure analysis; Flip-chip devices; Laminates; Reliability; Silicon; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location
San Diego, CA
Type
conf
DOI
10.1109/ECTC.2015.7159798
Filename
7159798
Link To Document