DocumentCode :
723173
Title :
20″ × 20″ panel size glass substrate manufacturing for 2.5D SiP application
Author :
Yu-Hua Chen ; Dyi-Chung Hu ; Tzvy-Jang Tseng
Author_Institution :
Unimicron Technol. Corp., Hsinchu, Taiwan
fYear :
2015
fDate :
26-29 May 2015
Firstpage :
1610
Lastpage :
1615
Abstract :
For high density interconnection IC packages of the future, the outlook is for thinner packages with higher routing densities. With that, managing the substrate warpage along processing steps becomes critical. Thin organic substrates face challenging warpage issues in manufacture and in chip assembly. Glass is one of the candidates that can be used in substrate to replace traditional organic substrate. The infrastructure of glass for LCD industry has already been developed for many years. Glass also has several superior properties than other substrate candidates, such as large panel size availability, adjustable CTE, high modulus, low dielectric constant, low dielectric loss and high insulating capability. Glass represents an attractive choice with potential of tailorable properties dependent on specific glass composition. By targeting the coefficient of thermal expansion (CTE), the CTE of glass can be made to match perfectly with silicon dies and for reliable package. In addition, the advantages of using glass for interposer derive from process flexibility for size and thickness since the glass fusion process provides sheets with dimensions of more than three meters. It is straight forward to provide glass substrate of almost any size needed. Large glass panels are ideally suited for fabrication of interposer where the panel process is expected to provide large number of interposers in each run compared with wafer processing. In addition, the two sided processing of the panel, the avoidance of CMP processes and without using liners further enable lower unit cost for the interposer. This paper demonstrates fabrication of glass interposer with through glass vias (TGV) daisy chain test vehicles using a 20” x 20” (508mm x 508mm) panel size glass substrate manufactured by substrate HVM (high volume manufacture) line for 2.5D SiP application. Daisy chain electrical measurement results of this glass substrate demonstrated good continuity and electric resi- tance. The reliability test results will also be described including pre-condition and thermal cycle test (TCT).
Keywords :
glass; integrated circuit reliability; substrates; system-in-package; three-dimensional integrated circuits; 2.5D SiP application; CMP processes avoidance; CTE; LCD industry; TCT; TGV daisy chain test vehicles; chip assembly; coefficient of thermal expansion; daisy chain electrical measurement results; glass fusion process; glass interposer fabrication; glass substrate; high density interconnection IC packages; large glass panels; process flexibility; processing steps; reliability test results; routing densities; silicon dies; substrate HVM line; substrate high volume manufacture line; substrate warpage; thermal cycle test; thin organic substrates; through glass vias daisy chain test vehicles; two sided processing; Accuracy; Fabrication; Glass; Reliability; Silicon; Substrates; Vehicles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location :
San Diego, CA
Type :
conf
DOI :
10.1109/ECTC.2015.7159812
Filename :
7159812
Link To Document :
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