Keynote speaker moving digital system design courses into the modern era, again

After 50+ years of digital system design being a course topic in Electrical Engineering Departments, the complexity of basic digital systems has risen greatly. Many so-called fundamental topics have fallen by the wayside as being irrelevant to mainstream design, and keeping courses current has always been a balancing act of evolving fundamental topics and available curricular time. Current digital system design uses language-based design methodologies for FPGAs and ASICs. These methodologies enable the design of larger, more exciting systems and almost instant feedback (with FPGAs or simulation) as to whether the designs work. But new fundamentals are needed to enable the efficient design of these systems. We will focus on how validation engineering has come to account for more than 50% of the industrial design flow and how it can be introduced into digital system design courses. We will discuss using SystemVerilog as a teaching platform since it directly integrates design and validation methodologies. Our experiences in introducing it into Sophomore, Junior, and Senior level logic design courses will be discussed.