Adjustable-Cost Overlays for Runtime Compilation

Previous work has shown that virtual architectures, or overlays, can greatly reduce lengthy FPGA compile times by providing application-specialized resources along with a flexible interconnect to support application changes. However, retaining full configurability of interconnect has also required significant area overhead. In this paper, we introduce a family of overlay architectures called super nets and an associated design methodology that uses data path merging to provide minimal-overhead support for multiple source net lists, and optionally provides an adjustable amount of source flexibility through a secondary interconnect network. We demonstrate that super nets can enable runtime compilation up to 13,000× faster than direct register-transfer logic (RTL) implementation, with up to 70% lower area than selectively enabled RTL data paths. Finally, we explore the design space of this family of overlays and show that it affords significant freedom to trade additional area for increased flexibility to support deviations from the source set, as introduced during development or by optimizations performed at runtime.