High Performance Memory Accesses on FPGA-SoCs: A Quantitative Analysis

FPGA-SoCs like Xilinx´s Zynq-7000 and Altera´s Generation 10 SoCs provide an integrated platform for HW/SW-co design applications. Computationally complex tasks can be implemented in the programmable logic part while control logic is implemented on the CPU. A potential bottleneck in such approaches is the interface latency and the data transfer throughput. Especially the data transfer to and from the memory subsystems can decrease the achievable performance significantly. Therefore, an analysis of the according subsystems of the Zynq-7000 has been performed in order to estimate the possible performance of HW/SW-codesigns with a special focus on two-dimensional memory accesses.