Correction to “Reconfigurable Processor for Energy-Efficient Computational Photography” [Nov 13 2908-2919]

In the above paper (ibid., vol. 48, no. 11, pp. 2908-2919, Nov. 2013), an error was made in reporting the operating voltage for the SRAMs. Section VI of the paper states: "The test chip, shown in Fig. 19, is implemented in 40 nm CMOS technology and verified from 25 MHz at 0.5 V to 98 MHz at 0.9 V with SRAMs operating at 0.9 V." The processor and the SRAMs were connected together and operated from the same supply voltage on chip. As a result, this statement should be modified as: "The test chip, shown in Fig. 19, is implemented in 40 nm CMOS technology and verified to be operational from 25 MHz at 0.5 V to 98 MHz at 0.9 V." The reference to the SRAM supply being at 0.9 V should be ignored in the table in Fig. 19.