DocumentCode :
723471
Title :
Layout optimizations to decrease internal power and area in digital CMOS standard cells
Author :
Innocenti, J. ; Julien, F. ; Portal, J.M. ; Lopez, L. ; Hubert, Q. ; Masson, P. ; Sonzogni, J. ; Niel, S. ; Regnier, A.
Author_Institution :
STMicroelectron. Rousset, Rousset, France
fYear :
2015
fDate :
25-29 May 2015
Firstpage :
1582
Lastpage :
1587
Abstract :
This paper presents several layout optimizations in order to decrease both, the internal power and the area of digital standard cells. A new D flip-flop (Dff) is designed using advanced design rules and lower active widths. Post-layout simulations are performed and the internal power of a new Dff is reduced by 20% while clock-to-Q delay remains unchanged. Indeed, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. The saturation current (IDSAT) is improved by 15% and 50% for NMOS and PMOS transistors, respectively. Moreover, the area of the new Dff is reduced by 20% by using lower active widths and new optimized design rules.
Keywords :
CMOS logic circuits; MOSFET; circuit optimisation; delay circuits; flip-flops; integrated circuit layout; logic design; random-access storage; D flip-flop; Dff; NMOS transistors; PMOS transistors; clock-to-Q delay; digital CMOS standard cells; e-NVM CMOS technology; embedded nonvolatile memory; internal power; layout optimizations; post-layout simulations; saturation current; Capacitance; Clocks; Delays; Layout; Logic gates; MOSFET; Standards; D flip-flop; Low power; carrier mobility enhancement techniques; design rules; standard cells; strained-silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2015 38th International Convention on
Conference_Location :
Opatija
Type :
conf
DOI :
10.1109/MIPRO.2015.7160523
Filename :
7160523
Link To Document :
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