Title :
A 3.5–9.5 GHz compact digital power amplifier with 39.3% peak PAE in 40nm CMOS technology
Author :
Qian, Huizhen Jenny ; Liang, Jian Orion ; Xun Luo
Author_Institution :
EWI, Delft Univ. of Technol., Delft, Netherlands
fDate :
March 30 2015-April 1 2015
Abstract :
A 3.5-9.5 GHz fully integrated digital power amplifier (DPA) with peak PAE of 39.3% in 40nm CMOS technology intended for a polar transmitter is presented. A compact wideband DPA design technique employing stacked stepped-impedance (SSI) transformer is firstly introduced to improve the power efficiency while tracking optimum load impedance in a wide bandwidth. This is the only reported wideband DPA operating above 3 GHz with a record fractional bandwidth (FBW) of 92.3%. The DPA exhibits peak output power of 22.2dBm and peak drain efficiency of 46.2% with 1.2V supply. The core chip size is only 0.22 mm2.
Keywords :
CMOS integrated circuits; power amplifiers; transmitters; CMOS technology; DPA design technique; FBW; SSI transformer; core chip size; digital power amplifier; peak PAE; polar transmitter; record fractional bandwidth; stacked stepped impedance; tracking optimum load impedance; CMOS integrated circuits; Impedance; RLC circuits; Radio frequency; Transforms; Wideband; Windings; Class-E; digital power amplifier (DPA); high efficiency; polar transmitter; stacked stepped-impedance (SSI) transformer; wideband;
Conference_Titel :
Wireless Symposium (IWS), 2015 IEEE International
Conference_Location :
Shenzhen
DOI :
10.1109/IEEE-IWS.2015.7164565
