Layout development of area efficient Lo-skewed even parity generator

Author

Singhal, Manas ; Mehra, Rajesh

Author_Institution

Dept. of Electron. & Commun., NITTTR, Chandigarh, India

fYear

2015

fDate

19-20 March 2015

Firstpage

614

Lastpage

618

Abstract

In digital transmission parity bit is added after every block of data. The use of parity allows the error free transmission of data. There are two types of parities, even parity and odd parity. In this paper an even parity generator´s layout has been developed and presented using 50nm CMOS technology. The layout of three bit Even Parity Generator is designed using unskewed and lo-skewed CMOS technologies and the results are compared in terms of power dissipation and area consumption. The proposed layout has shown an area efficiency of 58%. The Lo-skewed circuit also provide better Low-Transient as compared to unskewed circuit.

Keywords

CMOS integrated circuits; data communication; integrated circuit layout; CMOS; area consumption; digital transmission parity bit; error free data transmission; even parity generator; layout development; odd parity; power dissipation; size 50 nm; CMOS integrated circuits; CMOS technology; Computers; Generators; Layout; Logic gates; Very large scale integration; Area efficiency; CMOS; Parit; Skew; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Engineering and Applications (ICACEA), 2015 International Conference on Advances in

Conference_Location

Ghaziabad

Type

conf

DOI

10.1109/ICACEA.2015.7164764

Filename

7164764