DocumentCode
72562
Title
Jitter of Delay-Locked Loops Due to PFD
Author
Gholami, M. ; Ardeshir, Gholamreza
Author_Institution
Electr. Eng. Dept., Babol Noshirvani Univ. of Technol., Babol, Iran
Volume
22
Issue
10
fYear
2014
fDate
Oct. 2014
Firstpage
2176
Lastpage
2180
Abstract
In this paper, delay-locked loop´s (DLLs) jitter due to uncertainties in the phase frequency detector (PFD) is calculated. First, time-domain equations of the DLL are introduced. These equations are the key to obtaining a closed-form equation related to the jitter of DLL in presence of a noisy PFD. Jitter equations at the output of all stages are calculated theoretically. A DLL is designed in 0.18-μm CMOS technology to validate the obtained equations.
Keywords
CMOS integrated circuits; delay lock loops; detector circuits; jitter; time-domain analysis; CMOS technology; DLL; PFD; delay-locked loop; jitter equations; phase frequency detector; size 0.18 mum; time-domain equations; Clocks; Delays; Equations; Iterative closest point algorithm; Jitter; Mathematical model; Phase frequency detector; Delay-locked loop (DLL); jitter; phase noise; phase-locked loop (PLL); phase-locked loop (PLL).;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2013.2284501
Filename
6719546
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