Title :
Jitter of Delay-Locked Loops Due to PFD
Author :
Gholami, M. ; Ardeshir, Gholamreza
Author_Institution :
Electr. Eng. Dept., Babol Noshirvani Univ. of Technol., Babol, Iran
Abstract :
In this paper, delay-locked loop´s (DLLs) jitter due to uncertainties in the phase frequency detector (PFD) is calculated. First, time-domain equations of the DLL are introduced. These equations are the key to obtaining a closed-form equation related to the jitter of DLL in presence of a noisy PFD. Jitter equations at the output of all stages are calculated theoretically. A DLL is designed in 0.18-μm CMOS technology to validate the obtained equations.
Keywords :
CMOS integrated circuits; delay lock loops; detector circuits; jitter; time-domain analysis; CMOS technology; DLL; PFD; delay-locked loop; jitter equations; phase frequency detector; size 0.18 mum; time-domain equations; Clocks; Delays; Equations; Iterative closest point algorithm; Jitter; Mathematical model; Phase frequency detector; Delay-locked loop (DLL); jitter; phase noise; phase-locked loop (PLL); phase-locked loop (PLL).;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2013.2284501
