A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology

Not only PVT detection techniques but also a leakage compensation design are proposed to carry out 650/500 MHz 2×VDD output buffer in this paper. The proposed 2×VDD output buffer contains a novel PVTL (Process, Voltage, Temperature, Leakage) compensation circuit to resolve the problems in output buffers of nano-scale CMOS technologies. Particularly, the leakage compensation design is realized by an asynchronous control method to control current paths such that the switching loss and the slew rate in the output buffer can be reduced and increased, respectively. The proposed design has been realized and implemented by using a typical 40 nm CMOS process. The data rate is 650/500 MHz given 0.9/1.8 V supply voltage with a 20 pF load. The maximum slew rate is 3.5 (V/ns), and the core area is 0.052 × 0.213 mm².