A 1–20 GHz 400 ps true-time delay with small delay error in 0.13 µm CMOS for broadband phased array antennas

A CMOS broadband true-time delay (TTD) with 400 ps delay is presented. A second order all-pass network (APN) is used as the delay element to improve the delay-bandwidth tradeoff. Coarse delay tuning is realized with a 10-state trombone topology. To the best of our knowledge, this is the first time that the APN is used in the trombone topology. The fine tuning of the TTD is accomplished with the 3-bit switched APN structure. Both the delay path and the reference path are realized with the APN to minimize inter-state insertion loss (IL) variation. An extra continuous tuning stage is also implemented with the APN to realize broadband continuous tuning. The final TTD is fabricated in a standard 0.13 μm CMOS process. The core chip is 1.6 × 2.5 mm² and it consumes 2.2 mA to 5 mA from a 1.2 V supply for all the delay states. The maximum delay is 400 ps. The worst IL is 45 dB at 20 GHz for the largest delay. The measured input/output return loss is better than 13 dB across 1-20 GHz.