DocumentCode
726158
Title
2.4 GHz CMOS class D synchronous rectifier
Author
Dehghani, Soroush ; Johnson, Thomas
Author_Institution
Sch. of Eng., Univ. of British Columbia, Kelowna, BC, Canada
fYear
2015
fDate
17-22 May 2015
Firstpage
1
Lastpage
3
Abstract
A CMOS synchronous class D rectifier is implemented in 130 nm technology. The rectifier is designed to operate at 2.4 GHz and requires no external supplies for biasing. The measured RF to DC power efficiency is 30% for an input power of +10 dBm and the power efficiency is greater than 25% over a 12 dB dynamic range from 4-16 dBm. The area of the rectifier is 780 μm by 670 μm including input matching to 50 Ω and a DC output lowpass filter. Important aspects of the design include the feedback network for synchronous switching and injecting gate bias from the drain node.
Keywords
CMOS integrated circuits; UHF filters; low-pass filters; rectifiers; CMOS class D synchronous rectifier; RF-DC power efficiency; drain node; efficiency 30 percent; feedback network; frequency 2.4 GHz; injecting gate bias; lowpass filter; resistance 50 ohm; size 130 nm; synchronous switching; Power measurement; Rectifiers; Switching circuits; RF energy harvesting; class D amplifier; class D rectifier; wireless power;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Symposium (IMS), 2015 IEEE MTT-S International
Conference_Location
Phoenix, AZ
Type
conf
DOI
10.1109/MWSYM.2015.7167006
Filename
7167006
Link To Document