• DocumentCode
    726289
  • Title

    Jump test for metallic CNTs in CNFET-based SRAM

  • Author

    Feng Xie ; Xiaoyao Liang ; Qiang Xu ; Chakrabarty, Krishnendu ; Naifeng Jing ; Li Jiang

  • Author_Institution
    Dept. CS&E, Shanghai Jiao Tong Univ., Shanghai, China
  • fYear
    2015
  • fDate
    8-12 June 2015
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    SRAMs built on Carbon Nanotube Field Transistors (CNFET) are promising alternatives to conventional CMOS-based SRAMs, due to their advantages in terms of both power consumption and noise margin. However, non-ideal Carbon Nanotube (CNT) fabrication process generates metallic-CNTs (m-CNTs) along with semiconductor-CNTs (s-CNTs), rendering correlated faulty cells along the growth direction of the m-CNTs. Based on this phenomenon, we propose a novel testing algorithm for detecting m-CNTs, wherein consecutive write and read operations jump over multiple cells rather than marching through each and every cell, thereby significantly reducing the testing cost. The proposed jump test can be invoked before the march test to screen out those CNFET-SRAMs doomed to failure, and this can reduce the subsequent test overhead. Experimental results show that the proposed solution is able to achieve a high fault coverage with much less testing cost.
  • Keywords
    SRAM chips; carbon nanotube field effect transistors; low-power electronics; CNFET-based SRAM; carbon nanotube field transistors; faulty cell rendering; jump test; m-CNTs; metallic CNTs; noise margin; nonideal CNT fabrication process; nonideal carbon nanotube fabrication process; power consumption; semiconductor-CNTs; testing cost reduction; CNTFETs; Circuit faults; SRAM cells; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE
  • Conference_Location
    San Francisco, CA
  • Type

    conf

  • DOI
    10.1145/2744769.2744864
  • Filename
    7167199