Title :
TA-FTA: Transition-aware functional timing analysis with a four-valued encoding
Author :
Chang, Jasper C. C. ; Huang, Ryan H.-M ; Lin, Louis Y.-Z ; Wen, Charles H.-P
Author_Institution :
Dept. of Elec. Comp. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Timing analysis becomes profound for modern VLSI designs. Functional timing analysis (FTA) has emerged to eliminate false paths and provide better timing closure than traditional static timing analysis (STA). However, signal transitions effect, such as multiple input switching (MIS), which changes the pin-to-pin delay of a gate as well as the overall circuit delay, has not yet been considered in FTA. Therefore, a Transition-Aware FTA (TA-FTA) engine using a novel four-valued encoding for calculating true delay under the signal-transition effect is developed in this work. However, timing analysis becomes sophisticated once the signal-transition effect is concerned. Therefore, two techniques, cone separation and filtering (CSF) and quadratic dynamic search (QDS), are also proposed to speed up TA-FTA by more than two orders in time. Experimental results shows that after considering the MIS effect, in the benchmark circuits, the delay reported by our TA-FTA increases by 23% on average and by 38% for the worst case.
Keywords :
VLSI; encoding; filtering theory; integrated circuit design; logic circuits; logic design; synchronisation; timing; CSF; MIS effect; QDS; STA; TA-FTA engine; VLSI designs; cone separation and filtering; four-valued encoding; multiple input switching; overall circuit delay; pin-to-pin delay; quadratic dynamic search; signal transition effect; static timing analysis; timing closure; transition-aware functional timing analysis; very large scale integration; Benchmark testing; Delays; Encoding; Integrated circuit modeling; Logic gates; Switches; FTA;
Conference_Titel :
Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
DOI :
10.1145/2744769.2744914