Title :
A low power unsupervised spike sorting accelerator insensitive to clustering initialization in sub-optimal feature space
Author :
Zhewei Jiang ; Qi Wang ; Mingoo Seok
Author_Institution :
Columbia Univ., New York, NY, USA
Abstract :
Online unsupervised spike sorting or clustering is an integral component of implantable closed-loop brain-computer-interface systems. Robust clustering performance against various non-idealities such as poor initialization and order-of-arrival of inputs are desirable while meeting the minimal area and power requirements for implants. We explore an online and unsupervised spike-sorting algorithm utilizing a low-overhead feature screening process that improves feature discriminability in the use of sub-optimal features for reducing hardware complexity. Based on the algorithm, an accelerator architecture that performs feature screening and clustering is devised and implemented in a 65-nm high-VTH CMOS, largely improving clustering accuracy even with poor clustering initialization. In the post-layout static timing and power simulation, the power consumption and the area of the accelerator are found to be 2.17 μW/ch and 0.052 μm2/ch, respectively, which are 53% and 25% smaller than the previous designs, while achieving the required throughput of 420 sorting/s at the supply voltage of 300mV.
Keywords :
CMOS integrated circuits; brain-computer interfaces; pattern clustering; prosthetics; CMOS; accelerator architecture; clustering initialization; hardware complexity reduction; implantable closed-loop brain-computer-interface systems; low power unsupervised spike sorting accelerator; low-overhead feature screening process; online spike-sorting algorithm; online unsupervised spike sorting; post-layout static timing; power consumption; power simulation; robust clustering performance; size 65 nm; suboptimal feature space; unsupervised spike-sorting algorithm; voltage 300 mV; Algorithm design and analysis; Clocks; Clustering algorithms; Feature extraction; Power demand; Sorting;
Conference_Titel :
Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
DOI :
10.1145/2744769.2744779