DocumentCode :
726460
Title :
Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography
Author :
Hung-Chih Ou ; Kai-Han Tseng ; Yao-Wen Chang
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2015
fDate :
8-12 June 2015
Firstpage :
1
Lastpage :
6
Abstract :
Self-aligned double patterning (SADP) with complementary e-beam lithography (EBL) is one of the most promising hybrid-lithography techniques for sub-20nm designs. The complementary EBL mitigates the deficiencies of using a single cut mask in SADP. However, the low throughput and negative side effects of EBL might significantly increase the manufacturing costs and damage the symmetry properties in analog circuits. In this paper, we present the first work that considers SADP with EBL during analog placement to simultaneously optimize the area, wirelength, overlay errors, and e-beam shots. We first propose an overlay and cut conflict-aware SADP decomposition algorithm to optimize the overlay errors and e-beam shots in a layout. Then, a dynamic programming based module shifting technique is developed based on a symmetry-feasible slicing tree formulation to further minimize the differences of overlay errors and e-beam shots between symmetry modules during analog placement. To explore and obtain a desired placement, an analog placement flow is also presented. Experimental results show that our flow can effectively and efficiently reduce area, overlay errors, and e-beam shots while satisfying the symmetry constraints for analog placement.
Keywords :
cutting; dynamic programming; electron beam lithography; integrated circuit manufacture; masks; modules; cut conflict-aware SADP decomposition algorithm; cutting structure-aware analog placement; dynamic programming; e-beam lithography; e-beam shot; hybrid-lithography technique; manufacturing cost; module shifting technique; overlay error; self-aligned double patterning; single cut mask; symmetry property damage; symmetry-feasible slicing tree formulation; Algorithm design and analysis; Analog circuits; Color; Distortion; Heuristic algorithms; Layout; Lithography; Analog ICs; E-Beam Lithography; Physical Design; Placement; Self-Aligned Double Patterning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
Type :
conf
DOI :
10.1145/2744769.2744813
Filename :
7167375
Link To Document :
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