Title :
An embedded probabilistic extraction unit for on-chip jitter measurements
Author :
Bielby, Steven ; Roberts, Gordon W.
Author_Institution :
Integrated Microsyst. Lab., McGill Univ., Montreal, QC, Canada
Abstract :
As circuits become increasingly complex and testing time continues to increase, it is becoming more and more important to use built-in self-test techniques to ensure that the circuit is working according to its data sheet specifications. This paper presents an embedded test instrument in an IBM 130 nm CMOS technology, which allows for quick and easy probabilistic test evaluation of the bit-error ratio of a device-under-test.
Keywords :
CMOS integrated circuits; built-in self test; error statistics; jitter; IBM CMOS technology; bit error ratio; built-in self-test; complex time; data sheet specifications; device under test; embedded probabilistic extraction unit; embedded test instrument; on-chip jitter measurements; probabilistic test evaluation; size 130 nm; testing time; Bit error rate; Generators; Noise; Radiation detectors; System-on-chip; Threshold voltage; Timing;
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
DOI :
10.1109/ISCAS.2015.7168583
