Fast buffer delay estimation considering time-dependent dielectric breakdown

Author

Marranghello, Felipe S. ; Reis, Andre I. ; Ribas, Renato P.

Author_Institution

PGMICRO, Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil

fYear

2015

fDate

24-27 May 2015

Firstpage

177

Lastpage

180

Abstract

This paper presents a novel analytical delay model to perform fast estimation of signal delay propagation over buffer chain under time-dependent dielectric breakdown (TDDB) aging effect. The proposed model considers all gate-to-drain, gate-to-source and gate-to-bulk breakdowns effects, and relies on accurate modeling of TDDB. In comparison to SPICE simulation, based on BSIM4 transistor model, experimental results have shown an average error of 1.65%, whereas 98% of the cases present an estimation error of at most 5%.

Keywords

CMOS integrated circuits; buffer circuits; delay estimation; electric breakdown; BSIM4 transistor model; CMOS circuit; SPICE simulation; TDDB; aging effect; buffer chain; complementary metal oxide semiconductor; fast buffer delay estimation; gate-to-bulk breakdown effect; gate-to-drain breakdown effect; gate-to-source breakdown effect; signal delay propagation; time dependent dielectric breakdown; Delays; Electric breakdown; Integrated circuit modeling; Inverters; Logic gates; Semiconductor device modeling; Tin; CMOS design; TDDB; circuit reliability; gate delay model; oxide breakdown; time-dependent dielectric breakdown;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2015 IEEE International Symposium on

Conference_Location

Lisbon

Type

conf

DOI

10.1109/ISCAS.2015.7168599

Filename

7168599