Title :
An 8-bit column-shared SAR ADC for CMOS image sensor applications
Author :
Jin-Yi Lin ; Kwuang-Han Chang ; Chen-Che Kao ; Shih-Chin Lo ; Yan-Jiun Chen ; Pei-Chen Lee ; Chi-Hui Chen ; Chin Yin ; Chih-Cheng Hsieh
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
This paper presents an 8-bit asynchronous SAR ADC for CMOS image sensor applications in 130nm 1P4M technology. The proposed one-side merge-and-split switching effectively reduces the DAC switching energy because the reference voltage is halved. In addition, considering the bottom-plate parasitic capacitance, the proposed method can have better power efficiency compared to other methods. With 1.5V supply and Nyquist rate input, the prototype consumes 330μW at 16MS/s and achieves an ENOB of 7.21bit and a SFDR of 62.77dB, respectively. The resultant FoM is 139fJ/conv-step.
Keywords :
CMOS image sensors; analogue-digital conversion; low-power electronics; 1P4M technology; 8-bit asynchronous SAR ADC; CMOS image sensor applications; DAC switching energy; Nyquist rate input; bottom-plate parasitic capacitance; one-side merge-and-split switching; power 30 muW; power efficiency; reference voltage; voltage 1.5 V; word length 8 bit; Arrays; CMOS image sensors; CMOS integrated circuits; Capacitors; Frequency measurement; Parasitic capacitance; Switches; CMOS image sensors (CIS); Low power; successive approximation analog-to-digital converter (SAR ADC);
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
DOI :
10.1109/ISCAS.2015.7168630
