Title :
A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis
Author :
Jincai Liu ; Weixin Gai ; Liangxiao Tang
Author_Institution :
Dept. of Microelectron., Peking Univ., Beijing, China
Abstract :
A novel half-rate source-series-terminated (SST) transmitter in 65nm bulk CMOS technology is presented in this paper. Compared to previous half-rate SST transmitters, the proposed one consists of four binary-weighted slices increasing proportionally as 1x, 2x, 4x and 8x and the range of pre-emphasis level is increased greatly by the clock-match block to adapt to different channel. The half-rate transmitter can adjust the pre-emphasis level from 1.2dB to 23dB. The transmitter output impedance is adjustable from 33ohms to 64ohms. A power consumption of 24mW is measured at a transmit rate of 6 GB/s which is power-efficient compared to previous half-rate SST transmitter.
Keywords :
CMOS integrated circuits; calibration; electric impedance; power consumption; transmitters; CMOS technology; adjustable preemphasis; binary-weighted slice; bit rate 6 Gbit/s; clock-match block; complementary metal oxide semiconductor; half-rate SST transmitter; impedance calibration; power 24 mW; power consumption; size 65 nm; source-series-terminated transmitter; Clocks; Impedance; Impedance matching; Latches; Multiplexing; Timing; Transmitters; SST; adjustable pre-emphasis; impedance matching; voltage-mode transmitter;
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
DOI :
10.1109/ISCAS.2015.7168640