A higher order curvature corrected 2 ppm/°C CMOS voltage reference circuit

A low power, low temperature coefficient and ultra-stable higher order curvature compensated CMOS voltage reference circuit has been designed for use in energy harvesting applications. The circuit can provide a stable reference of 543 mV over a wide supply voltage range from 0.69V to 2.5 V with a line sensitivity of 0.05% / V. The circuit has been designed in 65 nm DTCMOS process. The novelty is the use of a simple higher order curvature correction topology to suppress the reference voltage variation at higher temperatures without any complex circuits. The proposed circuit achieves a temperature coefficient of 2ppm/°C over a wide temperature range of -30°C to +140°C. The power supply rejection ratio is -65 dB from DC to 1kHz and the power consumption at 1V is 60 nW. A calibration methodology is also briefly discussed with optimum results to reduce the reference voltage spread across corners.