A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic

Author

Song Jia ; Shilin Yan ; Yuan Wang ; Ganggang Zhang

Author_Institution

Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Beijing, China

fYear

2015

fDate

24-27 May 2015

Firstpage

890

Lastpage

893

Abstract

In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 25% reduction of power consumption is achieved by the proposed unit. In the 32/33 dual modulus prescaler, a critical path cutting scheme is introduced to improve speed to the limit decided by the divide-by-4/5 unit.

Keywords

clocks; frequency dividers; logic circuits; logic design; low-power electronics; power consumption; prescalers; 32-33 dual modulus prescaler; TSPC prescalers; critical path cutting scheme; divide-by-4-5 frequency divider; divide-by-4-5 unit; low-power high-speed 32-33 prescaler; power consumption; single-phase clock logic; true single-phase clock; Clocks; Frequency conversion; Logic gates; Power demand; Simulation; Topology; Transistors; TSPC; frequency divider; prescaler;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2015 IEEE International Symposium on

Conference_Location

Lisbon

Type

conf

DOI

10.1109/ISCAS.2015.7168777

Filename

7168777