Title :
A comprehensive optimization methodology for designing charge pump voltage multipliers
Author_Institution :
Micron Japan, Ltd., Tokyo, Japan
Abstract :
This paper proposes a comprehensive optimization methodology to simultaneously determine the clock frequency, area ratio of pump capacitor to switching circuit, number of stages, and capacitor size of integrated switched-capacitor charge pump voltage multipliers. Power efficiency of the charge pump is also discussed in various views. How the top and bottom plate parasitic capacitance and the threshold voltage of the switching circuit affect power efficiency is reviewed. The optimization methodology is demonstrated. Comparisons of the model with SPICE simulation results are also provided for validation.
Keywords :
charge pump circuits; switched capacitor networks; voltage multipliers; SPICE simulation results; capacitor size; clock frequency; integrated switched-capacitor charge pump voltage multipliers; optimization methodology; parasitic capacitance; power efficiency; pump capacitor; switching circuit; threshold voltage; Capacitors; Charge pumps; Clocks; Integrated circuit modeling; Optimization; SPICE; Switching circuits; Charge pump; Optimization; Power efficiency; Switched-capacitor; Voltage multiplier;
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
DOI :
10.1109/ISCAS.2015.7168894
